Semiconductor manufacturing: how the industry works
Semiconductor manufacturers turn circuit designs into tested chips. Their economics depend on process capability, manufacturing yield, equipment availability, and the demand for specific chips.
Scope and segments
Covers wafer fabrication, assembly, packaging, and testing. Chip design and semiconductor equipment are adjacent businesses, not interchangeable production stages. The operating model is global; company examples illustrate business structures rather than market-wide performance.
- Foundries
- Manufacture customers’ designs using qualified processes. The customer normally owns the chip design, while the foundry supplies process technology and production capacity.
- Integrated device manufacturers
- Combine design and manufacturing; some also sell foundry services. Memory, logic, analog, and power devices have different demand cycles and process needs.
- Assembly and test
- Package dies, make electrical connections, manage heat, and verify performance. Advanced packaging can become a separate capacity constraint.
10 companies to know
Illustrative companies spanning contract wafer fabrication, integrated device manufacturing, memory, and outsourced packaging and testing. This is not a ranking by revenue, capacity, or technological leadership.
Listed alphabetically. Names link to official sources. Checked . How we select examples.
-
Provides semiconductor packaging, testing, and system assembly through its operating companies. It illustrates how specialized contractors turn fabricated dies into packaged, qualified components.
-
GlobalFoundries
Contract wafer fabrication
Manufactures chips for customers using technologies including radio frequency, power, and silicon photonics. Its foundry model separates customer product design from operating fabrication facilities.
-
Infineon Technologies
Power semiconductors
Supplies power semiconductors using silicon, silicon carbide, and gallium nitride technologies. These products illustrate manufacturing requirements shaped by energy conversion and control applications.
-
Intel
Fabrication and advanced packaging
Operates wafer fabrication and advanced packaging facilities through Intel Foundry. Its manufacturing services illustrate the relationship between process technology, packaging, testing, and customer qualification.
-
Micron Technology
Memory and storage
Produces semiconductor memory and storage products, including DRAM and NAND. Its manufacturing network illustrates the process investment and product specialization involved in memory production.
-
Samsung Electronics
Memory and foundry services
Its semiconductor business supplies memory, processors, image sensors, and foundry services. It illustrates a company participating in several chip categories with different customer requirements.
-
SK hynix
Memory semiconductors
Supplies DRAM, NAND storage, and solid-state drives for computing and connected devices. Its portfolio illustrates the distinction between memory components and assembled storage products.
-
STMicroelectronics
Integrated device manufacturing
Designs, manufactures, and sells integrated circuits, handling much of production internally. It illustrates the integrated manufacturer model across wafer fabrication, packaging, and product support.
-
Texas Instruments
Analog and embedded chips
Designs, manufactures, tests, and sells analog and embedded processing chips. These components illustrate manufacturing tied to power management, sensing, communications, and control functions.
-
TSMC
Contract wafer fabrication
Manufactures customers’ semiconductor designs and provides advanced packaging services. Its dedicated foundry model illustrates the coordination required between chip designers, fabrication processes, and production capacity.
How it works
Follow the main sequence. Actual operating models may combine or outsource individual stages.
- 1
Design and qualify
Translate the design into masks and a process-compatible layout. Qualification establishes that the design and manufacturing process work together.
- 2
Build the wafer
Repeat deposition, lithography, etching, and other operations to form devices and interconnects. Inspection feeds measurements back into process control.
- 3
Probe and select
Test dies while they remain on the wafer. A finished wafer is not equivalent to a wafer full of saleable chips.
- 4
Package and test
Separate dies, assemble packages, and perform final testing. Sorting by performance can produce several saleable product grades.
How money moves
- Revenue or funding unit
- A processed wafer, a packaged device, or a contracted assembly/test operation, depending on the supplier.
- Who pays
- Fabless designers buy foundry capacity; device companies buy packaging and testing. Electronics manufacturers ultimately purchase chips directly or through distributors.
Main costs
- Equipment and facilities
- Depreciation, maintenance, and cleanroom infrastructure create substantial costs even when production is below plan.
- Process execution
- Materials, specialist labor, electricity, water treatment, and repeated tool steps accumulate before the finished chip can be sold.
Assets and investment
A fab requires specialized equipment and infrastructure. A capacity expansion is useful only if it supports the processes and products customers actually need.
The cash cycle
Wafers spend time in production before shipment and payment. A demand change can strand expensive work in progress or finished inventory.
The economic mechanism
Yield is the share of potential dies meeting requirements. Higher yield spreads wafer-processing cost over more good dies. Utilization spreads factory overhead across more production. These are different levers: a full fab with poor yield can still have bad economics.
Inside the operation
Measures that matter
| Measure | What it measures | Why it matters |
|---|---|---|
| Die yield | Good dies divided by tested candidate dies, with the test boundary stated. | Links defect and performance problems to saleable output. |
| Cycle time | Elapsed time from wafer start to completion for a defined route. | Long queues tie up cash and slow learning. |
| Tool availability | Scheduled time when a specified tool can process work. | A bottleneck tool can constrain the whole fabrication route. |
What shapes the industry
A process label alone does not make two factories interchangeable. Design rules, libraries, reliability qualification, and packaging choices bind a product to a production system. Moving an established design can require redesign and validation, creating switching costs.
Demand is segmented. Excess capacity for one type of memory or mature process does not automatically resolve a shortage in another process or advanced packaging step. A useful capacity map therefore follows compatible process routes rather than simply counting factories.
Who it connects to
These relationships describe typical flows. They are not a list of every supplier or customer.
Buys from / depends on
- Electric utilities
Supply the continuous power needed for process equipment and controlled facilities.
- Water utilities
Provide feedwater that fabs further treat to process-specific purity.
Supplies / serves
- Automobile manufacturing
Uses control, sensing, connectivity, and power-management devices.
- Telecommunications
Uses chips in network equipment and devices.
Substitutes and alternatives
- Alternative chip architectures
Different designs may deliver the required function, but qualification, software compatibility, and performance constrain substitution.
How yield changes cost per good die
Illustrative calculation
The inputs below are hypothetical. They explain a mechanism and are not industry benchmarks or a forecast.
Assumptions
- Illustrative wafer-processing cost: $12,000, excluding packaging, development, and corporate overhead.
- A wafer has 600 candidate dies; compare 70% and 85% die yield.
Calculation
- At 70% yield: 600 × 0.70 = 420 good dies; $12,000 ÷ 420 = $28.57 per good die.
- At 85% yield: 600 × 0.85 = 510 good dies; $12,000 ÷ 510 = $23.53 per good die.
The same wafer cost produces more saleable output. This is a yield calculation, not a claim about chip selling prices or total manufacturing cost.
What changes when…
Demand falls after a capacity expansion.
- Wafer starts decline while much equipment depreciation and facility cost continue.
- Cost per processed wafer rises if fixed overhead is allocated across fewer wafers.
- Discounting can recover some volume but does not necessarily restore margin; management must separate temporary inventory correction from lasting product weakness.
What to watch
- Process-specific utilization
- Customer inventory and order cancellations
- Yield on new products
A qualitative scenario based on the operating model, not a quantitative prediction.
Risks and misconceptions
- Yield excursion
- A process deviation can affect many lots before final testing reveals the problem; traceability determines which material must be held.
- Demand and capacity mismatch
- Orders can retreat faster than factories and equipment can be repurposed, depressing utilization.
- Infrastructure interruption
- Power, water, or critical-material disruption can stop tightly sequenced production and damage work in progress.
Sources: [2]. See source scope below.
Common misconceptions
- The smallest process node is best for every chip.
- Cost, voltage, reliability, analog performance, and lifecycle requirements can favor other processes.
Sources and scope
Primary references anchor the factual mechanisms below. Operating models, relationship choices, and worked examples are editorial synthesis. Linked sources do not constitute endorsement.
- How microchips are madeASML
Fabrication sequence, inspection, packaging, and the distinction between chipmaker business types.
- Six crucial steps in semiconductor manufacturingASML
Process precision, pattern transfer, deposition, etching, and packaging; updated 2023.
- Dedicated IC FoundryTSMC
Primary company description of manufacturing customer-owned products under the foundry model.
- 2022 NAICS definition: Semiconductor and Related Device ManufacturingU.S. Census Bureau
U.S. classification boundary and the code mapping; a partial match is not equivalence between this article and every establishment in the code.
Process descriptions draw on the cited primary sources. Business-model interpretation is editorial synthesis; worked-example figures are illustrative assumptions, not industry benchmarks. Regulation and commercial arrangements vary by jurisdiction. Classification mappings use the U.S. 2022 NAICS edition; partial mappings indicate overlapping rather than identical scope.
Classification references
- NAICS 2022: 334413 — Semiconductor and Related Device Manufacturing (partial mapping).
From understanding to operating
Try this workflow with ERP.AI
Review planned production windows alongside run observations, downtime intervals, unit output, and quality decisions to investigate equipment performance in a defined semiconductor production process.
2 Run it with Proto
Get the desktop agent, then return to the app page to continue setup.